1. Field of the Invention
The present invention relates to a method and structure for generating a voltage on an integrated circuit chip. More specifically, the present invention relates to a voltage supply created by charging and discharging capacitors formed on an integrated circuit chip.
2. Description of the Prior Art
FIG. 1 is a circuit diagram of a prior art charge pump 100 used to generate a voltage on an integrated circuit chip. Charge pump 100, which is commonly known as a voltage multiplier circuit, is described in the article by J. Dickson, entitled "On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique", IEEE J. Solid State Electronics, Vol. SC-11, June 1976, pp. 374-378. Charge pump 100 makes use of capacitors 101-108 which are interconnected by diodes 111-119. Capacitors 101, 103, 105 and 107 are coupled in parallel to clock signal Ck1, and capacitors 102, 104, 106 and 108 are coupled in parallel to clock signal Ck2. Clock signals Ck1 and Ck2 are 180 degrees out of phase with each other. Each node 121-128 exhibits stray capacitance, designated by capacitors 131-138.
An input voltage V.sub.IN is provided to diode 111 and an output voltage V.sub.OUT is generated at the output terminal of diode 119. Diodes 111-119 can be either conventional diodes or diodes fashioned from an MOS transistor (See, the article by J. Witters, G. Groeseneken, H. Maes, entitled "Analysis and Modeling of On-Chip High-voltage Generator Circuits for Use in EEPROM Circuits" IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, October 1989).
Charge pump 100 operates by pumping charge along diodes 111-119 as the capacitors 101-108 are successively charged and discharged during each half clock cycle. The voltages at nodes 121-128 are not reset after each pumping cycle. Consequently, the average potential of nodes 121-128 progressively increases from node 121 to node 128.
Charge pump 100 has several disadvantages. First, each of diodes 111-119 experiences a series voltage drop. The sum of these voltage drops limits the voltage generated at the output terminal of diode 119. In addition, it takes many clock cycles to charge capacitors 101-108 to provide the desired output voltage level. This latency exists because charge pump 100 sequentially charges one capacitor at a time, beginning with capacitor 101 and ending with capacitor 108. The output terminal of diode 119 does not reach the desired voltage until capacitor 108 is charged.
Furthermore, each of capacitors 101-108 must maintain a high voltage in order to supply the desired voltage. Capacitor 108 experiences the highest voltage, which is equal to the voltage at the output terminal of diode 118. The high voltages applied to capacitors 101-108 cause stress on the gate oxides of the capacitors and can cause gate oxide breakdown.
Accordingly, it is desired to have a voltage generating circuit which is capable of quickly generating a desired output voltage. It is also desired to have a voltage generating circuit which does not require the application of a high voltage across the charged capacitors. It is also desired to have a voltage generating circuit which generates the same voltage as prior art voltage generating circuits using less capacitance.